1. Field of the Invention
The present invention generally relates to a method for forming a non-salicide p+ polysilicon resistor to replace the N-well resistor in semiconductor manufacture procedure to reduce the RC timing delay.,
2. Description of the Prior Art
A static random access memory (SRAM) is widely used in integrated circuits, and plays an especially important role in the electronic industry. The unanimous target for the industries is to fabricate a device with reduced dimensions and high quality. A load resistor is one of the devices that constitute a SRAM cell and is usually made of lightly doped or undoped polysilicon.
Many semiconductor devices and integrated circuits are designed to operate over wide temperature ranges. For example, circuits may be specified to perform correctly at all temperatures in a given temperature range. In some application this range may be rather large, for example from as low as xe2x88x9250xc2x0 C. or lower up to 125xc2x0 C. or possibly even higher.
In semiconductor physics, the mobility is a measure of the ease of carrier motion within a semiconductor structure. A low mobility implies the carriers inside the semiconductor are suffering a relatively large number of motion-impeding collisions. A large mobility, on the other hand, implies the carriers are zipping along with comparative ease. As is known, the resistivity is inversely proportional to the mobility. In other words, as the mobility goes up, the resistivity will go down; and as the mobility goes down, the resistivity will go up.
The mobilities and resistivities of semiconductor structures will depend upon the temperature, doping concentrations and other factors. In very low doped samples, for example, carrier mobilities monotonically decrease as the temperature is increased. For higher sample dopings, however, the temperature dependence becomes increasingly more complex.
Referring to FIG. 1, a NAND 10 is connected to a transducer. A N-well resistor 12 which is connected between NAND 10 and metal (RM) 14, and capacitor 16. The capacitor 16 is connected device 18. The device comprises high speed device such as static random access memory (SRAM).
N-well resistance is widely used in circuit design and has some advantages such as layout benefit Unfortunately, it has apparent temperature dependence and increases RC delay time with temperature.
For the forgoing reasons, there is a necessary for a resistor for replacing N-well resistor. It would obtain good benefit to reduce the RC delay that would compensate the inherent MOS mobility deceleration at high temperature.
In accordance with the present invention, the present invention provides a non-salicide p+ polysilicon resistor used to replace a N-well resistor to solve problems in resistor capacitance (RC) corresponding to the temperature in the traditional procedures.
The second object of the present invention is to decrease temperature dependence of the resistor and to get better layout benefit by using a non-salicide p+ polysilicon resistor to replace a N-well resistor.
The third object of the present invention is to decrease a resistance at high temperature by using a non-salicide p+ polysilicon resistor to replace a N-well resistor.
The further object of the present invention is to reduce the RC timing delay, which compensates the inherent MOS mobility deceleration at high temperature, by using a non-salicide p+ polysilicon resistor to replace a N-well resistor.
In order to achieve the above object, the present invention provides a method for forming a non-salicide p+ polysilicon resistor used to replace a N-well resistor to solve problems in resistor capacitance corresponding to the temperature in the traditional procedures. At first, the present invention provides a substrate, wherein a material of the substrate is polysilicon. Then p+ ions are implanted into the substrate to form a p+ polysilicon resistor in the substrate, wherein the p+ ions belong to III group elements and comprise boron ions. In the implanting p+ ions procedure, a dosage of p+ ions is about 2xc3x971015cmxe2x88x922 to 4xc3x971015cmxe2x88x922 and an energy of the implanted p+ ions is about 12 kev to 13 kev. Because there is no salicide layer on the p+ polysilicon resistor region, the p+ polysilicon resistor of the present invention is a non-salicide p+ polysilicon resistor. Using the non-salicide p+ polysilicon resistor of the present invention can decrease temperature dependence of the resistor and get better layout benefit. Using the non-salicide p+ polysilicon resistor of the present invention can also decrease a resistance at high temperature. Using the non-salicide p+ polysilicon resistor of the present invention can further reduce the RC timing delay, which compensates the inherent MOS mobility deceleration at high temperature.